The present invention relates to methods of forming oxides layers in semiconductor structures.
A widely used isolation technique in semiconductor structures is silicon trench isolation (STI), shown in FIG. 5. A field oxide 4 narrows into an oxide layer 10 on a silicon substrate 2. FIGS. 1–4 illustrate the steps used to prepare the structure shown in FIG. 5. Thermal oxidizing forms an oxide layer (SiO2) 10 on the silicon substrate 2, followed by depositing a silicon nitride (Si3N4) layer (isolation nitride) 6 using low pressure chemical vapor deposition (LPCVD) to form the structure shown in FIG. 1. Next, a photoresist layer 12 is applied, and patterned using a mask. Etching of those portions of the silicon nitride layer, thermal oxide and silicon substrate not covered by the photoresist layer, in a single operation, opens a trench 14, giving the structure shown in FIG. 2.
The photoresist layer is then stripped, and the substrate is cleaned. An oxide layer 16 is then deposited into the trench and across the surface of the structure by chemical vapor deposition (CVD), producing the structure shown in FIG. 3. Chemical-mechanical polishing (CMP) planarizes the surface, leaving the oxide layer 16 only in the trench, as shown in FIG. 4. The silicon nitride layer is removed, to produce the structure shown in FIG. 5. Typically, further processing will include ion implantation through the oxide layer 10, using it as a screen oxide, to form source/drain regions, and then removal of the screen oxide followed by growth of a gate oxide layer on the silicon substrate. At this point, completion of a semiconductor device, by the formation of gates, contacts, metallization, etc., may be carried out, and the semiconductor device may then be incorporated into an electronic device.
During CMP to planarize the surface of the structure, the center to edge uniformity across the wafer is very poor. Consequently, the thickness of the silicon nitride layer varies across the wafer. The silicon nitride layer is typically removed by etching with a phosphoric acid etch. Since the etch is continued for a time sufficient to remove the nitride layer, over etching is necessary to ensure that all of the silicon nitride is removed. Furthermore, during LPCVD silicon nitride is deposited on both the front and back sides of the wafer; over etching is necessary to ensure remove of the silicon nitride on the back side of the wafer, to avoid interference with the stepper.
The silicon nitride/silicon oxide selectivity of the silicon nitride etching changes as the bath of phosphoric acid is used. A fresh phosphoric acid bath will etch silicon oxide slowly, and as the bath is used, the rate of etching of silicon oxide will slow down, stop and eventually begin to deposit oxide. The thickness of the oxide layer (typically used as a screen oxide during ion implantation) is usually 125 Å when initially formed, will have a variable thickness at the end of this process, depending on the age of the phosphoric acid bath used during the etching of the silicon nitride layer, and the amount of over etching. The variable thickness of the screen oxide will affect the formation of the source/drain regions, leading to inconsistent threshold voltages (Vt) for the transistors formed on the wafer.